Class 12 Computer Science Notes: Computer Hardware (Chapter 2)
Master Chapter 2 of Class 12 Computer Science. Understand memory types, CPU architecture, bus systems, I/O interfacing, DMA, and pipeline processing with key concepts and exam PYQs.
Students treat Computer Hardware as a list of definitions to memorise. They learn what RAM stands for and what a CPU does, but they cannot explain how these components interact. When exam questions ask about data flow or system trade-offs, they have no framework to answer.
1. Types of Memory ā Properly Distinguished
| Memory Type | Volatile? | Location | Purpose |
|---|---|---|---|
| Cache | Yes | Inside/near CPU | Stores recently accessed data for fastest CPU retrieval |
| RAM | Yes | On motherboard | Currently running programs and data |
| ROM | No | On motherboard | Firmware like BIOS ā read-only, permanent |
| Virtual Memory | Yes | Hard disk | Extension of RAM using disk space ā not hardware |
ā ļø Watch Out! ā ROM Is Primary Storage
Students classify ROM as secondary storage because it is non-volatile. But secondary storage means not directly accessible by the CPU. ROM is directly accessed by the CPU (it holds the BIOS/firmware the CPU reads at startup), so it is primary storage.
Non-volatile ā secondary. Direct CPU access = primary storage.
2. The CPU and the Fetch-Decode-Execute Cycle
The CPU does not just "perform calculations." It follows a precise cycle for every single instruction:
- Fetch: The Control Unit reads the next instruction from memory at the address stored in the Program Counter (PC).
- Decode: The instruction is interpreted to determine what operation is required.
- Execute: The ALU (Arithmetic Logic Unit) or other units carry out the operation.
The Program Counter increments automatically after each fetch to point to the next instruction. Students who do not know this cycle cannot explain what the Control Unit does or what happens during a branch instruction.
3. The Bus System
The Three Buses
- Data Bus: Carries actual data between components. Width determines how much data moves in one transfer.
- Address Bus: Carries memory addresses. Width determines how much memory the CPU can address. A 32-bit address bus ā 2Ā³Ā² addressable locations.
- Control Bus: Carries coordination signals (read/write, interrupt requests, clock signals).
A standard board question: "What determines the maximum addressable memory?" Answer: the width of the address bus.
4. I/O Interfacing Techniques
| Technique | How It Works | Best For |
|---|---|---|
| Polling | CPU periodically checks if device is ready | Simple, slow devices |
| Interrupt | Device signals CPU when ready; CPU responds | Events that need quick response |
| DMA | Device transfers data directly to memory without CPU involvement | High-speed devices (disks, NIC) |
DMA advantage: The CPU is free to do other work while the DMA controller handles the data transfer. Students who do not know DMA cannot explain why it is used for disk I/O over polling.
5. Pipeline vs. Parallel Processing
- Pipeline Processing: Splits instruction execution into stages (fetch, decode, execute). While one instruction executes, the next is decoded and the one after is being fetched. Single processor, multiple overlapping stages.
- Parallel Processing: Multiple processors or cores execute genuinely independent instructions simultaneously. Multiple processors, truly simultaneous execution.
Students confuse these because both make computers faster. The key difference: pipelining overlaps stages of the same instruction stream; parallel processing runs separate streams at the same time.
Summary: Key Facts at a Glance
| Concept | Key Fact |
|---|---|
| ROM classification | Primary storage (directly accessible by CPU) |
| Virtual memory | Not hardware ā disk space used as RAM extension |
| Max addressable memory | Determined by address bus width |
| DMA advantage | CPU-free data transfer for high-speed devices |
| Pipeline vs. Parallel | Pipeline = 1 CPU, overlapping stages; Parallel = multiple CPUs |
Practice Questions (PYQs)
- Distinguish between RAM and ROM. Why is ROM classified as primary storage even though it is non-volatile?
- What is virtual memory? How does it differ from physical RAM? What is its disadvantage?
- Explain the fetch-decode-execute cycle. What is the role of the Program Counter in this cycle?
- Differentiate between polling and interrupt-driven I/O. Give one situation where each would be preferred.
- Explain the difference between pipeline processing and parallel processing. Why is parallel processing not simply a faster version of pipelining?